產(chǎn)品分類(lèi) > DSP > DSP > MSC8157SVT1000A

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MSC8157SVT1000A

廠(chǎng)商:
Freescale
類(lèi)別:
DSP
包裝:
-
封裝:
FCPBGA 783 29SQ3.55P1.0
無(wú)鉛情況/ROHS:
無(wú)鉛
描述:
Qual'ed 8157 NE FG 1GHz 0 to

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  • 參數
  • 描述
參數 數值
Export Control Classification Number (US) 3A991
Floor Life 168 HOURS
Halogen Free Yes
Leadtime (weeks) 12
Maximum Time at Peak Temperature (s) 30
Package Length (nominal) (mm) 29.000
Moisture Sensitivity Level (MSL) 3
Number of Reflow Cycles 3
Pin/Lead/Ball Count 783
2nd Level Interconnect e1
Part Number MSC8157SVT1000A
POQ Container BOX
RoHS Certificate of Analysis (CoA) Download RoHS CoA Report
Tape & Reel No
Budgetary Price($US) 100 @ $158.95 each
Minimum Package Quantity (MPQ) 1
Peak Package Body Temperature (PPT)(°C) 245
Application/Qualification Tier COMMERCIAL, INDUSTRIAL
Device Weight (g) 11.10460
Package Description and Mechanical Drawing FCPBGA 783 29SQ3.55P1.0
Package Thickness (nominal) (mm) 3.575
Micron Size (μm) .04
Preferred Order Quantity (POQ) 180

The MSC8157 targets high-bandwidth highly computational DSP applications and is optimized for 3G-LTE (FDD and TDD), UMTS and WiMAX systems. The device includes a combination of fully programmable DSP cores and powerful hardware acceleration to provide best-in-class performance, power efficiency, connectivity and cost-effectiveness.


Features

  • Core frequency 1 GHz operating at up to 48000 MMACS with six SC3850 cores. The core subsystems support several large areas of memory/cache, a memory controller and interrupt controller
  • CLASS high-speed non-blocking interconnect fabric to provide optimal throughput between all internal device blocks
  • The MAPLE-B2 supports Turbo decoding including rate matching supporting up to 330 Mb/s for 3GLTE, up to 300 Mb/s for WiMAX and up to 260 Mbps in UMTS at eight full iterations; Turbo encoding: information bits encoding including rate matching up to 900 Mbps for 3GLTE and WiMAX and up to 450 Mbps for UMTS; Viterbi decoding up to 200 Mbps for K=9, zero tailing and up to 175 Mbps for K=7 tail biting; FFT/iFFT processing supporting up to 960 Msps; DFT/iDFT processing supporting up to 630 Msps; CRC check and insertion supporting up to 10 Gbps.
  • DMA controller with 16 bidirectional channel pairs
  • Internal data profiling for optimizing data throughput during development
  • Dual RISC core QUICC Engine subsystem supporting two SGMII/RGMII ports and serial peripheral interface (SPI)
  • HSSI complex with OCN fabric, two 4-channel DMA controllers, two Serial RapidIO® ports, an enhanced messaging unit and 10 SerDes lanes multiplexing two Serial RapidIO x4/x2/x1 interfaces up to five Gbaud, PCI Express® x4/x2/x1 interface, six CPRI channels, and two SGMIIs.
  • Eight programmable hardware semaphores to manage resources
  • Other serial interfaces: UART, timers, I?2;C, GPIO, interrupts and JTAG
  • Power supplies: Core power: 1-volt nominal, I/O power, 1.0-volt, 1.5-volt and 2.5-volt nominal
  • Flip chip-plastic ball grid array (FC-PBGA), 783-ball, 1 mm pitch, 29 mm × 29 mm.
  • Optional security engine (E version only) to provide data encryption/decryption capability. Supports Kasumi f8/f9, AES-128 and AES-256, SNOW and other protocols.
    • WiMAX
    • Base Station and Other Infrastructure Equipments
    • WCDMA

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